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Synthesizable VHDL Design for FPGAs By Eduardo Bezerra, Djones Vinicius Lettnin
Download PDF Synthesizable VHDL Design for FPGAs By Eduardo Bezerra, Djones Vinicius Lettnin
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- Sales Rank: #7841890 in Books
- Published on: 2013-10-22
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x .44" w x 6.14" l, .91 pounds
- Binding: Hardcover
- 157 pages
From the Back Cover
This book provides a gradual description of very-high-speed integrated circuits hardware description language (VHDL), targeting the design of digital systems to be implemented in field-programmable gate array (FPGA) platforms. It is organized in a very didactic way. The adopted methodolgy was matured over 20 years of teaching experience in the subject. The examples in the book were planned targeting two FPGA platforms, one used widely around the world and the other one developed by a Brazilian company.
About the Author
Dr. Eduardo Bezerra is a Researcher and Lecturer of Computer Engineering at Universidade Federal de Santa Catarina (UFSC), where he is with the Department of Electrical Engineering since 2010. He received his Ph.D. in Computer Engineering from the University of Sussex (Space Science Centre), England, UK, in 2002. His research interests are in the areas of embedded systems, computer architecture, reconfigurable systems (FPGAs), space applications, software & hardware testing, fault tolerance and microprocessor applications.
Djones Lettnin has Master´s in Electric Engineering at Catholic University of Rio Grande do Sul (2004), Brazil, and Sc.D. in Computer Engineering at the Eberhard Karls University of Tübingen (2009), Germany. In August 2011 he became Professor at Federal University of Santa Catarina, Brazil. Since August 2012 he is first coordinator of the Cadence Academic Network in Latin America. His main interests are in design and functional verification of hardware and embedded software with main focus on: modeling of embedded systems, digital design, verification based on assertions, semiformal and formal verification using model checking.
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